EAGLE is a schematic capture and printed circuit board (PCB) design package that includes a powerful User Language. Using that language, it is possible to write User Language Programs (ULPs) that can capture information from schematic editor file and produce an arbitrary output. We wrote a ULP that generates a Spice netlist. This document contains instructions for using the program.

First step in generating a Spice netlist is to draw a schematic. There are a few simple rules to follow.

• Nodes in Spice netlist are equivalent to nets in schematic. Nets are automatically labeled using labels N$1, N$2, ..., N$n. These names are translated in node names by dropping a dollar ($) sign, thus giving names N1, N2, ..., Nn. Whenewer a user wants to force his or her own node name, a corresponding net should be renamed by schematic NAME command, and the name could be made visible by attaching a LABEL to the net. In order to be able to rename a net, or attach a label to it, the net has to be be visible. Schematic editor automatically places a net between two elements that are connected directly through their pins (i.e. pin a of the first element is placed directly on pin b of the second element), but such net is not visible. In order to make it visible the two elements should be pulled apart a bit.
• The reference node should be named GND or 0 (zero).
• Each element in a schematic can have two strings attached to it. Those are >NAME and >VALUE. Names are automatically generated for all elements and usually start with the letter that is also required by Spice for that type of element. If that is not the case, the name should be edited. The value of an element is either entered by a user or automatically selected from one of the EAGLE libraries. Both strings, name and value, are directly copied in the netlist, the first being placed before, and the second after the node list:

  >NAME N1 N2 ... Nn >VALUE

• If any pin of an element is not connected to a net, a questionmark (?) will be placed in the generated netlist in place of the missing connection.
• For virtual devices, such as controlled sources, which cannot be used in PCB design directly, a special library was added to the EAGLE package named spice.lbr.

A Spice netlist is generated from a schematic by running the spice ULP from command line. The syntax of the program execution is

RUN spice.ulp [working directory path [master document name [output file name]]]

Working directory is the one where output file (by default with the same name as the schematic file but the .cir extension) will be generated and where the master document resides (named "master.cir" by default).

• A master document is a .cir file that contains all the neccessary data for the circuit analysis (control blocks, includes of the libraries, etc) except for the netlist itself which is generated by the spice ULP program. Master document must .INCLUDE the generated netlist file and all the used model and subcircuit libraries. It is important that at the time of generation of the netlist all the used subcircuits be included, so the ULP is able to properly order subcircuit nodes.
• Subcircuits and Models. As mentioned above, subcircuits should be accessible through master document (contained either in the master document itself or any document .INCLUDEd by the master document) at the netlist generation time. The name of the subcircuit should be entered only as the device's >VALUE in a schematic.
• Hand-Editing the Net List. After generating a netlist it is possible to edit it using any text editor. If the text typed by hand is placed in a separate line where the first character is plus (+) sign, this text will be preserved if the automatic netlist generation is executed again. Hand-edited lines should be placed immediately after the element entry (no comment lines are allowed) and will be preserved only if the element name still exists during the next autogeneration of the netlist. If the element is deleted from the schematic or its name is changed, the hand-edited lines belonging to that element will be lost.
• Here is an example (example.zip 33KB). See the DESCRIPTION (project) file for details.