10.5.6. Customization example: generating MOS mismatch parameters

In Section Customization example: netlisting MOS devices as subcircuits we customized the netlister behavior so that instead of generating builtin MOS devices it produced a netlist where MOS transistors were subcircuits defined in file mosmm.inc. Manufacturing introduces variation in the MOS transistor properties. Therefore two identically designed MOS transistors do not share the same characteristics. This effect is called mismatch and is modelled with additional parameters VTMM and U0MM. Random process variations are transformed to these two parameters in such manner that if one treats VTMM and U0MM as two independent normally distributed random variables with zero mean and standard deviation 1 the correct joint probability distribution of MOS model parameters are reproduced.

In simulations parameters VTMM and U0MM are used by various analyses. To make them accessible their values are taken from global parameters. This means that two fields must be added to every MOS transistor in the miller.sch schematic. It is more simple to change the netlisting rules for MOS transistors with the following netlister.json file.

        "Mapping": [
			null, "PMOS",
				"Parameters": [ "w", "l", "m" ],
				"OutPattern": "#REF() (#PINS()) #MODEL() #PARAM() #PNV() vtmm={#REFORIG()vt} u0mm={#REFORIG()u0} #PV(Specification)",
				"SpiceDevice": "subcircuit",
				"PinMap": [ 1, 2, 3, 4 ],
				"NamePrefix": "X",
				"ValueField": null
			null, "NMOS",
				"Parameters": [ "w", "l", "m" ],
				"OutPattern": "#REF() (#PINS()) #MODEL() #PARAM() #PNV() vtmm={#REFORIG()vt} u0mm={#REFORIG()u0} #PV(Specification)",
				"SpiceDevice": "subcircuit",
				"PinMap": [ 1, 2, 3, 4 ],
				"NamePrefix": "X",
				"ValueField": null

For a transistor named m1 in the schematic #REFORIG()vt expands to m1vt. This way the vtmm parameter of m1 can be set via the m1vt global circuit parameter. To avoid neltlisting VTMM and U0MM values that are specified as component fields these two parameters are not included in the Parameters member of the device mapping.

By netlisting the miller.sch schematic we get the following netlist.

* SPICE OPUS netlister for KiCad
* (c)2017 EDA Lab FE Uni-Lj
* Netlister : KiCad -> Spice Opus
* Config    : /mnt/data/Data/pytest/demo/kicad/05-genmmpar/netlister.json
* Source    : /mnt/data/Data/pytest/demo/kicad/05-genmmpar/miller.sch
* XML input : /mnt/data/Data/pytest/demo/kicad/05-genmmpar/miller.xml
* Output    : /mnt/data/Data/pytest/demo/kicad/05-genmmpar/miller.inc
* Date      : Wed 13 Oct 2021 01:57:24 PM CEST
* Tool      : Eeschema 5.1.9+dfsg1-1
* Sheet 1   : / -- miller.sch

.subckt miller inp inn out vdd vss

* Sheet: /
xm2 (net003 net002 vss vss) nmosmod param: w=79.46u l=1.91u m=1 vtmm={m2vt} u0mm={m2u0} 
xm1 (net002 net002 vss vss) nmosmod param: w=20.80u l=0.32u m=1 vtmm={m1vt} u0mm={m1u0} 
xm3 (out net002 vss vss) nmosmod param: w=60.23u l=0.32u m=1 vtmm={m3vt} u0mm={m3u0} 
xm6 (net005 net005 vdd vdd) pmosmod param: w=90.43u l=3.92u m=1 vtmm={m6vt} u0mm={m6u0} 
xm7 (net004 net005 vdd vdd) pmosmod param: w=90.43u l=3.92u m=1 vtmm={m7vt} u0mm={m7u0} 
xm8 (out net004 vdd vdd) pmosmod param: w=83.01u l=0.20u m=2 vtmm={m8vt} u0mm={m8u0} 
i1 (vdd net002)  dc=100u
r1 (out net001) r=67.6k 
c1 (net001 net004) c=13.5p 
xm4 (net005 inn net003 vss) nmosmod param: w=67.29u l=3.97u m=1 vtmm={m4vt} u0mm={m4u0} 
xm5 (net004 inp net003 vss) nmosmod param: w=67.29u l=3.97u m=1 vtmm={m5vt} u0mm={m5u0} 


For the simulation all the generated global circuit parameters must be defined. We do that in the top level schematic topdc.sch. There are two ways how to add parameter values to a schematic.

The first if to use the PARAM component from the KiCad pyopus library. One PARAM component must be added for every global parameter we must define. This makes the schematic portable so that when support for other simulators will be added these parameter definition will be netlisted correctly.

The second one is less portable but also involes less clicking. We add a text block to the toplevel schematic with the .param` statements that define the required global parameters. The disadvantage of this approach is that it is simulator specific. Due to the simulator syntax it sould be fine for Spice Opus and HSPICE, but not for Spectre.


Top level circuit definition that defines the global parameters generated by the netlister.

Note that the text block with the .control block is renamed to Text2. It is dumped at the bottom of the netlist file, just before .end. The text block with global parameter definitions is named Text1 and is dumped before any elements are netlisted.

The following toplevel circuit netlist is obtained.

* SPICE OPUS netlister for KiCad
* (c)2017 EDA Lab FE Uni-Lj
* Netlister : KiCad -> Spice Opus
* Config    : /home/arpadb/pytest/demo/kicad/05-genmmpar/netlister.json
* Source    : /home/arpadb/pytest/demo/kicad/05-genmmpar/topdc.kicad_sch
* XML input : /home/arpadb/pytest/demo/kicad/05-genmmpar/topdc.xml
* Output    : /home/arpadb/pytest/demo/kicad/05-genmmpar/topdc.cir
* Date      : Tue Apr 19 09:35:27 2022
* Tool      : Eeschema 6.0.4+dfsg-1~bpo11+1
* Sheet 1   : / -- topdc.kicad_sch

.include miller.inc
.lib 'cmos180n.lib' tm
.include mosmm.inc

* Verbatim block Text1 from sheet /
.param m1vt=0
.param m1u0=0
.param m2vt=0
.param m2u0=0
.param m3vt=0
.param m3u0=0
.param m4vt=0
.param m4u0=0
.param m5vt=0
.param m5u0=0
.param m6vt=0
.param m6u0=0
.param m7vt=0
.param m7u0=0
.param m8vt=0
.param m8u0=0

* Sheet: /
cl1 (net001 0) c=1p 
e1 (out 0 net001 0) gain=1 
r1 (inn in) r=1meg 
r2 (out inn) r=1meg 
rl1 (net001 0) r=100meg 
vcom1 (inp 0)  dc=0
vdd1 (vdd 0)  dc=0.9
vin1 (in 0)  dc=0 ac=1
vss1 (vss 0)  dc=-0.9
x1 (inp inn net001 vdd vss) miller   

* Verbatim block Text2 from sheet /
destroy all
delete all

dc vin1 -0.9 0.9 lin 500
plot v(out) vs v(inp,inn) xl -5m 2m

set units=degrees
ac dec 100 1 1g
plot db(v(out)/v(inp,inn)) unwrap(phase(v(out)/v(inp,inn)))


Demo files for this section can be found here.